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| (R) L64733C/L64734 Tuner and Satellite Receiver Chipset Datasheet The L64733C/734 chipset is designed for satellite broadcast digital TV. It is compliant with the European digital video broadcast (DVB-S) standard, as well as the technical specifications for DSS systems. The L64733C/734 chipset forms a complete "L-band-to-bits" system. A typical application of the L64733C/734 chipset is satellite digital TV reception in accordance with the ETS 300 421 standard. Figure 1 shows the L64733C/734 chipset satellite receiver implemented in a typical satellite receiver set-top decoder. Figure 1 Set-Top Box Block Diagram 27 MHz VCXO FLASH SDRAM-B SDRAM-A Expansion Bus Analog Audio Analog CVBS Analog Y/C Analog RGB Digital Video Satellite RF Signal L64733C Tuner L64734 Demodulator OP AMPs SC2000 Single-Chip Source Decoder Serial Bus IEEE 1284 Smart Cards RS232-C Interface CODEC I/R Rx & Tx GPIO Pins The L64733C Tuner IC directly down-converts the satellite signal from L-band to baseband; it includes an on-chip synthesizer. Using frequency information programmed into its configuration registers, the L64734 Satellite Receiver generates control signals for the L64733C synthesizer. The L64734 also controls the programming of the low-pass filters on the February 2001 Copyright (c) 2000, 2001 by LSI Logic Corporation. All rights reserved. 1 L64733C and generates dual automatic gain control (AGC) voltages for the two-stage automatic gain control on the L64733C. A simplified chipset block diagram is shown in Figure 2. Figure 2 Select RF Input RF Output RF Switch L64733C/734 Simplified Block Diagram L64733C Mixer, Down Conversion Baseband Filter Control Signals Control Modules for Synthesizer and Filter IOUT QOUT L64734 Dual ADC Demodulator Host Microcontroller Microcontroller Interface Error Correction Descrambler MPEG Output Figure 3 shows a more detailed chipset block diagram. The L64733C accepts the RF In L-Band signal input from the satellite low noise block (LNB) feed. The L64733C handles a fully loaded raster of transponder signals from 925 MHz to 2175 MHz. RF In is internally matched to 75 ; it requires no matching network between the cable connector and the L64733C input pins, except for a DC-blocking capacitor. The L64733C uses the L64734 INSEL signal to select the appropriate RF function (Normal or Loop-Through Mode). 2 L64733C/L64734 Tuner and Satellite Receiver Chipset Figure 3 Detailed Chipset Block Diagram L64733C Xtal Osc / by 8 RF Switch Phase Detect. Charge Pump To external Loop Filter 4-7.26 MHz RF In RF Out Tank Circuit LOBUF LODIV Amp Quadrature Down-Converter VCO X2 /32/33 or /1/2 2 2 2 90 Fc 2 FDOUB INSEL PSOUT PLLIN FLCLK QOUT AGC1 AGC2 L64734 Synthesizer Control Module AGC Control Carrier Loop Control BPSK/QPSK Demodulator Timing Loop Control Filter Control Module MOD CPG I Dual ADC Interpolator/Decimation Filter Matched Filter Output Control 1/T Q Microcontroller Data and Address Bus Clk (from L64734 on-chip PLL) FEC Decoder Pipeline External Microcontroller Interface Microcontroller Data and Address Bus Channel Output (MPEG-2 Transport Stream) Descrambler ReedSolomon Decoder Convolutional Deinterleaver ReedSolomon Synchronizer Viterbi Decoder Viterbi Synchronizer L64733C/L64734 Tuner and Satellite Receiver Chipset IOUT 2 3 The RF signal is sent to a variable gain stage controlled by the L64734 AGC1 signal. The L64734 adjusts AGC1 in conjunction with AGC2 to maximize the SNR of the RF In signal while maintaining proper levels at the baseband outputs (IOUT and QOUT). The signal then is fed to two mixers in the quadrature demodulator. The mixers are fed with local oscillator signals that are offset by 90 degrees from one another. The quadrature demodulator converts the frequency of the RF In signal directly to baseband while splitting the signal into quadrature I and Q signal paths. The baseband signals pass through a pair of variable gain amplifiers, controlled through the AGC2 pin by the L64734. The signals then pass through a pair of seventh-order filters for antialiasing. The filter shape is seventh-order Butterworth, followed by a single-pole delay equalizer. The L64734 FLCLK signal controls the filter cutoff frequency, which is related to the baud rate. The filtered baseband output signals are fed to differential output stages at IOUTp, IOUTn, QOUTp, and QOUTn. The baseband outputs of the L64733C are sent to the L64734 to be digitized by the analog-to-digital converter (ADC). Then, they are sent to a BPSK/QPSK demodulator, filtered, and sent to the L64734 forward error correction (FEC) decoder pipeline, which outputs an MPEG-2 transport stream. The frequency synthesizer functionality is split between the L64733C and L64734. The Synthesizer Control Module resides on the L64734 and generates control signals for the L64733C Tuner IC frequency synthesizer. The Synthesizer Control Module also contains programmable counters for the synthesizer feedback loop. The L64733C provides analog functions for the frequency synthesizer, the RF local oscillator, and the crystal reference oscillator. Tuning oscillator signals are generated for the mixers in the 925-2175 MHz range, with a 0.625 MHz step size when using a 5 MHz crystal reference. The on-chip VCO tuning frequency is 543-1088 MHz. To tune channels from 925-1086 MHz, the L64734 disables the frequency doubler (X2 block) on the L64733C. To tune channels from 1086-2175 MHz, the L64734 enables the frequency doubler. The L64733C can improve half-harmonic rejection. It requires special programming of the frequency doubler control pin (FDOUB), which now 4 L64733C/L64734 Tuner and Satellite Receiver Chipset has 3-state operation (see the "Synthesizer Control Interface" section on page 20). The VCO requires an external resonant tank circuit, which includes varactor diodes to vary the frequency of oscillation. The VCO signal is fed to the Prescaler block before being passed deferentially through the PSOUTp and PSOUTn pins to the L64734. The L64734 MODp and MODn differential signals control the divider ratio for the Prescaler block. The L64734 dynamically changes the divide ratio to ensure that the tuning step size is not affected by the divider. The L64734 contains programmable counters to further divide the signal frequency before it is fed back to the L64733C through the PLLINp and PLLINn pins. The crystal reference oscillator frequency is divided by eight and fed to the phase detector. The phase detector generates a current signal proportional to the difference in phase between PLLINp, PLLINn, and the divided crystal frequency. A charge pump circuit generates current that controls pins CP and FB, and an external transistor to buffer the L64733C against the tuning voltage (28 V). The current is passed through a discrete loop filter and is converted to a tuning voltage that drives the external varactor diodes for the VCO tank circuit. A frequency controlled loop is formed. Changing the frequency divider ratios in the L64734 registers varies the VCO frequency. See Figure 7, on page 23, for more details regarding the external circuitry for the VCO, crystal oscillator, charge pump, tank circuitry, and frequency-controlled loop. The chipset provides maximum integration and flexibility for system designers at a minimum cost. The number of external components required to build a system is minimal because the synthesizer, variable rate filters, and clock and carrier loops are integrated into the two devices. L64733C/L64734 Tuner and Satellite Receiver Chipset 5 Features and Benefits The following subsections provide a list of system and chipset features. System Features * * * * * * Direct down-conversion Integrated programmable cut-off low-pass filters for variable-rate operation Dual AGC for optimizing performance with respect to intermodulation and noise Integrated synthesizer Integrated quadrature amplitude and phase imbalance compensation RF Loop-Through Chipset Features * * * * * * * * * * * DVB and DSS system specifications support BPSK/QPSK demodulation rates from 1 to 45 Mbaud Matched filter (square root raised cosine filter with roll off factor of 20% or 35%) Antialiasing filters for operation from 1 to 45 MBaud without switching external SAW filters or the need for low-pass filters On-chip digital clock synchronization On-chip digital carrier synchronization, featuring a frequency sweep capability for signal acquisition Autoacquisition demodulator mode and tuner control through an on-chip microcontroller Integrated Phase-Locked Loop (PLL) for clock synthesis, allowing the use of a fundamental mode crystal Fast channel switching mode Power estimation for AGC Programmable Viterbi decoder module for rates 1/2, 2/3, 3/4, 5/6, 6/7, and 7/8 6 L64733C/L64734 Tuner and Satellite Receiver Chipset * * * * * * * * * (204/188), (146/130) Reed-Solomon decoder Autosynchronization for Viterbi decoder Programmable synchronization for deinterleaver, Reed-Solomon decoder, and descrambler Bit error monitoring for channel performance measurements Deinterleaver (DVB and DSS) Serial host interface compatible with the LSI Logic Serial Control bus interface Power-down mode On-chip dual differential 6-bit ADCs Supports Synchronous Parallel Interface protocol for FEC data output Chipset Interconnections Figure 4 illustrates the signals between the L64733C and L64734. L64733C/L64734 Tuner and Satellite Receiver Chipset 7 Figure 4 Chipset Interconnection Diagram L64734 AGC1 AGC2 CPG1 CPG2 FDOUB FLCLK INSEL MODp MODn PLLINp PLLINn XTLOUT AGC1 AGC2 XCTR[0] XCTR[1] FDOUB FLCLK INSEL MODp MODn PLLINp PLLINn XOIN PSOUTp PSOUTn IVINp IVINn QVINp QVINn Prescaler Signals L64733C Control Signals Control Signals Prescaler Signals PSOUTp PSOUTn IOUTp IOUTn QOUTp QOUTn Channel Data Signals Channel Data Signals L64733C Signal Descriptions This section describes the L64733C signals. Figure 5 shows the interface diagram of the L64733C. An "n" suffix (for example, ERROROUTn) designates an active LOW signal. Names of differential signals are designated with a "p" suffix for the noninverting side (for example, QOUTp), and with an "n" suffix for the inverting side (for example, QOUTn). 8 L64733C/L64734 Tuner and Satellite Receiver Chipset Figure 5 L64733C Interface Diagram RFINn AGC1 AGC2 CPG1 CPG2 FDOUB FLCLK IDCp IDCn INSEL LOBUF LODIV MODp MODn PLLINp PLLINn QDCp QDCn CP FB RF Signals RFINp RFOUT XTLn XTLp XTLOUT CFLT TANKn TANKp VRLO IOUTn IOUTp QOUTn QOUTp PSOUTn PSOUTp Oscillator Signals Control Signals Channel Data Signals Prescaler Signals Charge Pump Signals As shown in Figure 5, the L64733C has the following major interfaces: * * * * * * RF Oscillator Channel Data Prescaler Control Charge Pump The following signal descriptions are listed according to the major interface groups. RF Signals The L64733C can accept an RF input signal and loop it to RFOUT, as determined by an on-chip RF switch. L64733C/L64734 Tuner and Satellite Receiver Chipset 9 RFINp, RFINn RF Input Input The RFIN differential signals form the 75 input. Connect the RFINp signal through a series 100 pF capacitor to a 75 F video connector and the RFINn signal through a series 75 resistor and 100 pF capacitor to ground. RFOUT RF Output Output The RFOUT signal is a 75 output that is active when the INSEL input is deasserted. When active, the signal at RFOUT is a copy of the RFIN signal. Oscillator Signals The L64733C has two internal oscillators, a crystal oscillator and a tank oscillator. CFLT Bias Voltage Bypass Bidirectional Connect the CFLT pin as shown in Figure 7 on page 23. TANKp, TANKn Oscillator Tank Port Input Connect the TANKp and TANKn pins as shown in Figure 7 on page 23. VRLO XTLp, XTLn Local Oscillator Regulator Bypass Bidirectional Connect the VRLO pin as shown in Figure 7 on page 23. Crystal Oscillator Port Input Connect the XTLp and XTLn pins as shown in Figure 7 on page 23. Crystal Out Output This signal provides a buffered clock reference frequency for driving the L64734 XOIN pin. XTLOUT Channel Data Signals The following signals are the channel data signals from the L64733C to the L64734. IOUTp, IOUTn I Channel Baseband Data Output The IOUT differential signals form the in-phase data provided to the L64734. 10 L64733C/L64734 Tuner and Satellite Receiver Chipset QOUTp, QOUTn Q Channel Baseband Data Output The QOUT differential signals form the quadrature-phase data provided to the L64734. Prescaler Signals The following signals are the prescaler outputs from the L64733C to the L64734. PSOUTp, PSOUTn Prescaler Output When the LOBUF signal is LOW, the PSOUT differential signals are the L64733C prescaler outputs. When LOBUF is HIGH, the Local Oscillator (LO) buffer (50 ) feeds the PSOUT differential signals. The programmable counters on the L64734 are clocked on the rising edge of the PSOUT signal. Control Signals The following signals, some of which are generated by the L64734 IC, control the mode of operation of the L64733C IC. AGC1 Automatic Gain Control 1 Input The AGC1 signal is a high-impedance input from the L64734 that controls RF AGC circuitry. The AGC1 voltage has a range of 0.5 V to 4.8 V. Automatic Gain Control 2 Input The AGC2 signal is a high-impedance input from the L64734 that controls RF AGC circuitry. Charge Pump Gain The CPG[2:1] signals set the charge pump gain according to the table below. Charge Pump Current (typ), mA CPG1 0 0 1 1 CPG2 0 1 0 1 FB HIGH 0.1 0.3 0.6 1.8 FB LOW -0.1 -0.3 -0.6 -1.8 AGC2 CPG[2:1] Input L64733C/L64734 Tuner and Satellite Receiver Chipset 11 FDOUB Frequency Doubler Input When FDOUB is asserted, the L64733C local oscillator frequency is internally doubled and fed to the mixers. When FDOUB is deasserted, the oscillator frequency is not doubled before being fed to the mixers. Bit 6 of register 79, group 4 (APR 79), controls the L64734 FDOUB output pin, which enables or disables the frequency doubler on the L64733C. The FDOUB pin is set as shown in the table below, where Fswitch is the frequency at which the frequency doubler is enabled or disabled. Frequency 925 MHz-Fswitch Fswitch-1680 MHz 1680-2175 MHz FDOUB APR 79[6] 0 1 1 TRI APR 79[2] 0 1 0 FDOUB Pin LOW 3-state HIGH This method of control preserves the compatibility with the L64733B, which is not affected by 3-stating the FDOUB pin. FLCLK Filter Clock Input The FLCLK signal is a low amplitude, self-biased clock input. The frequency of the FLCLK signal multiplied by 16 is the baseband filter's -3 dB frequency. I-Channel DC Offset Correction Input Connect a 0.1 F or larger capacitor between the IDCp and IDCn signals. RF Port Input Select Input When the INSEL signal is asserted, the L64733C is in normal mode. When the INSEL signal is deasserted, the L64733C is in Loop-Through mode. In this mode, the RFIN signal is looped through out to the RFOUT signal and the L64733C local oscillator is shut off. Local Oscillator Buffer Select Input Asserting LOBUF causes the external PLL mode to be in effect, the local oscillator (LO) buffer to be enabled, and the LO signal to be sent out to the PSOUT pins according to the division ratio selected with the LODIV signal. When IDCp, IDCn INSEL LOBUF 12 L64733C/L64734 Tuner and Satellite Receiver Chipset LOBUF is deasserted, the internal PLL mode is in effect, and the PSOUT pins are driven from the 32/33 prescaler. LODIV Local Oscillator Buffer Division Ratio Input When the LODIV signal is asserted, the local oscillator (LO) buffer division ratio is set to 1; when it is deasserted, the ratio is set to 2. MODp, MODn Prescaler Modulus Input The MOD differential signals form a Positive Emitter Coupled Logic (PECL) input that sets the prescaler modulus. When the MODp signal is positive with respect to the MODn signal, the prescaler modulus is set to 32 (divide by 32). When the MODn signal is positive with respect to the MODp signal, the prescaler modulus is set to 33 (divide by 33). PLLINp, PLLINn Phase Detector Input The PLLIN differential signals form the phase detector input and are connected to the L64734 PLLINp and PLLINn output signals. See the L64734 PLLINp and PLLINn descriptions in the "Synthesizer Control Interface" section. QDCp, QDCn Q-Channel DC Offset Correction Input Connect a 0.1 F or larger capacitor between the QDCp and QDCn signals. Charge Pump Signals The following signals are outputs from the L64733C charge pump. CP FB Charge Pump Output Connect the CP signal as shown in Figure 7, on page 23. Feedback Charge Pump Transistor Drive Output Connect the FB signal as shown in Figure 7, on page 23. L64734 Signal Descriptions This section describes the L64734 signals. Figure 6 shows the interface diagram of the L64734. L64733C/L64734 Tuner and Satellite Receiver Chipset 13 Figure 6 L64734 Interface Diagram IBYPASS[5:0] IVINn IVINp QBYPASS[5:0] QVINn QVINp CLK XOIN XOOUT LCLK LP2 PCLK PLLAGND PLLVDD PLLVSS IDDTN RESET XCTR_IN XCTR[3:0] AGC1 AGC2 FLCLK INSEL BCLKOUT CO[7:0] COEn DVALIDOUT ERROROUTn FSTARTOUT INTn SADR[1:0] SCLK SDATA FDOUB MODp MODn PLLINp PLLINn PSOUTp PSOUTn VREF_LVDS RESO_LVDS FBUFVDD FBUFVSS IBIAS ADCVDDI ADCVDDQ ADCVSSI ADCVSSQ Channel Interface Channel Data Output Interface Channel Clock Interface Microcontroller Interface PLL Interface Synthesizer Control Interface Control Signals Interface AGC Control Interface Tuner Control Interface ADC Interface As shown in Figure 6, the L64734 has the following major interfaces: * * * * * * * * * * Channel Channel Clock PLL Control Signals ADC AGC Control Channel Data Output Microcontroller Synthesizer Control Tuner Control 14 L64733C/L64734 Tuner and Satellite Receiver Chipset The following signal descriptions are listed according to the major interface groups. Channel Interface The Channel Interface is the input path to the L64734 satellite receiver. The two signals IVIN and QVIN are the I and Q streams from the satellite tuner circuit. The CLK signal strobes in the data signals. IBYPASS[5:0] I Channel Data Input The IBYPASS[5:0] signals form the digital received I channel data input bus, which supplies the I Stream to the L64734 when the ADC is bypassed. The setting of particular register bits in the L64734 controls the bypass. IVINp, IVINn I Channel Data Input The IVINp and IVINn differential signals form the analog received I channel data input bus, which supplies the I stream to the L64734. QBYPASS[5:0] Q Channel Data Input The QBYPASS[5:0] signals form the digital received Q channel data input bus, which supplies the Q Stream to the L64734 when the ADC is bypassed. The setting of particular register bits in the L64734 controls the bypass. QVINp, QVINn Q Channel Data Input The QVINp and QVINn differential signals form the analog received Q channel data input bus, which supplies the Q stream to the L64734. Channel Clock Interface The Channel Clock Interface consists of the clock and crystal oscillator signals. CLK IVIN/QVIN Input Clock Input CLK is a positive, edge-triggered clock that strobes input data to the L64734. L64733C/L64734 Tuner and Satellite Receiver Chipset 15 XOIN Crystal Oscillator In Input The XOIN pin provides a crystal oscillator or external reference clock input. Normally, a 15 MHz crystal is connected to the XOIN pin. Crystal Oscillator Out Output The XOOUT pin is the crystal oscillator output pin. XOOUT Phase-Locked Loop (PLL) Interface The internal PLL generates the signals to operate the ADC, Demodulator, and FEC modules. LCLK Decimated Clock Output Output The L64734 internal clock generation module generates the LCLK signal. LCLK is derived from CLK by dividing by the value of the CLK_DIV2 register parameter. Input to VCO Input The LP2 signal is the input to the internal voltage-controlled oscillator. Normally, it is connected to the output of an external RC filter circuit. PLL Clock Output Output The L64734 internal PLL clock synthesis module generates the PCLK signal. The reference crystal connected between the XOIN and XOOUT pins drives the PLL. The PLL clock synthesis module can be configured to generate a PCLK rate that is appropriate for all data rates. PLL Analog Ground Input PLLAGND is the analog ground pin for the PLL module and normally is connected to the system ground plane. PLL Power Input PLLVDD is the power supply pin for the PLL module and normally is connected to the system power (VDD) plane. PLL Ground Input PLLVSS is the ground pin for the PLL module and normally is connected to the system ground plane. LP2 PCLK PLLAGND PLLVDD PLLVSS 16 L64733C/L64734 Tuner and Satellite Receiver Chipset Control Signals Interface The Control Signals Interface controls the operation of the L64734 and is not associated with any particular interface. IDDTN Test Input The IDDTN pin is an LSI Logic internal test pin. Tie the IDDTN pin LOW for normal operation. Reset Input This active-HIGH signal resets all internal data paths. Reset timing is asynchronous to the device clocks. Reset does not affect the configuration registers. Control Input Input The XCTR_IN pin is an external input control pin. It is sensed by reading the XCTR_IN register bit. Control Output/Sync Status Flag Output The XCTR[3] signal indicates the synchronization status for one of three synchronization modules in the L64734 or the XCTR[3] field in Group 4, APR 55. The three modules are the Viterbi Decoder, Reed-Solomon Deinterleaver (DI/RS), and Descrambler. For each of the three synchronization outputs, the asserted XCTR[3] signal indicates that synchronization is achieved for the sync module chosen using the SSS[1:0] register bits. When deasserted, the signal indicates an out-of-synchronization condition. Output Control Output The XCTR[2:0] pins are external output control pins. They are set by programming particular register bits. XCTR[2] is mapped to CPG1 and XCTR[0] is multiplexed with CPG2 when used with the L64733C Tuner IC. When the on-chip serializer generates a serial 2- or 3-wire protocol on the XCTR[2:0] pins, the mapping is XCTR[2] = EN, XCTR[1] = SCL, and XCTR[0] = SDA. RESET XCTR_IN XCTR[3] XCTR[2:0] Analog-to-Digital Converter (ADC) Interface The ADC module converts the incoming IVIN and QVIN signals into an internal 6-bit digital representation for processing. The following pins support the ADC module. L64733C/L64734 Tuner and Satellite Receiver Chipset 17 ADCVDDI/Q ADC Power Input ADCVDDI/Q are the analog power supply pins for the ADC module and normally are connected to the system power (VDD) plane. ADC Analog Ground Input ADCVSSI/Q are the analog ground pins for the ADC module and normally are connected to the system ground plane. Analog Supply Input FBUFVDD is the analog supply pin for the on-chip reference voltage generator. This pin normally is connected to the system power (VDD) plane. Analog Ground Input FBUFVSS is the analog ground pin for the on-chip reference voltage generator. This pin normally is connected to the system ground (VSS) plane. ADC Bias Current Output This is the bias current for the ADC module. Connect this output to a 39 k resistor, and connect the other side of the resistor to ground. ADCVSSI/Q FBUFVDD FBUFVSS IBIAS AGC Control Interface The AGC Control Interface contains signals used for power control. AGC1, AGC2 Power Control Output The AGC1 and AGC2 signals are the positive modulated output used for power control. These signals can each drive an external passive RC filter that feeds a gain control stage for dual-stage AGC. For a single stage AGC, AGC1 can be used, and has the same functionality as the PWRP pin on the L64724. Channel Data Output Interface The Channel Data Output Interface is the output path from the L64734. It typically is connected to the input of the transport demultiplexer in a set-top decoder application. 18 L64733C/L64734 Tuner and Satellite Receiver Chipset BCLKOUT Byte Clock Out Output The BCLKOUT output signal is a strobe that indicates valid data bytes on the CO[7:0] bus when the L64734 is in Parallel Channel Output mode. The BCLKOUT signal cycles once every valid output data byte and is used by the transport demultiplexer to latch output data from the L64734 at the BCLKOUT rate. The BCLKOUT signal must be disregarded in Serial Channel Output mode. Channel Data Out Output The CO[7:0] signals form the decoded output data port. When the OF bit is 1 (Group 4, APR17), the L64734 operates in the Parallel Channel Output mode. In this mode, the L64734 outputs the channel data as 8-bit wide parallel data on the CO[7:0] signals. In Serial Channel Output mode (OF = 0), the L64734 outputs the channel data as serial data on CO[0]. The data is latched on each bit clock cycle. The chronological ordering in Serial Channel output mode is MSB oldest, LSB newest. Channel Output Enable Input When asserted, the COEn signal enables the ERROROUTn, CO[7:0], DVALIDOUT, BCLKOUT, and FSTARTOUT signals. Operation of the receiver continues regardless of the state of the COEn signal. Valid Data Out Output The DVALIDOUT signal indicates that the CO[7:0] signals contain the corrected channel data. New data is valid on the CO[7:0] signals when the DVALIDOUT signal is asserted. DVALIDOUT is not asserted during the propagated check and GAP bytes. The DVALIDOUT signal is deasserted after the FEC_RST register bit (Group 4, APR 55) is set to one. CO[7:0] COEn DVALIDOUT ERROROUTn Error Detection Flag Output The L64734 asserts the ERROROUTn signal at the beginning of each frame that contains an uncorrectable error, and deasserts it at the end of the frame if the error condition is removed. The ERROROUTn signal is aligned with the output data stream and is asserted after the FEC_RST register bit is set. L64733C/L64734 Tuner and Satellite Receiver Chipset 19 FSTARTOUT Frame Start Output Output The L64734 asserts the FSTARTOUT signal during the first bit of every frame with valid data in Serial Channel Output mode and during the first byte in Parallel Channel Output mode. FSTARTOUT is valid only when the DVALIDOUT signal is asserted. The FSTARTOUT signal is deasserted after the FEC_RST register bit is set. Microcontroller Interface The Microcontroller Interface connects the L64734 to an external microcontroller. INTn Interrupt Output The L64734 asserts INTn when an internal unmasked interrupt flag is set. The INTn signal remains asserted during the interrupt condition, and the interrupt flag is not masked. Serial Address Input The SADR[1:0] signals are the two programmable bits of the serial address for the L64734. Serial Clock Bidirectional SCLK is the serial clock pin for a two-wire serial protocol. Serial Data Bidirectional SDATA is the serial data pin for a two-wire serial protocol. SADR[1:0] SCLK SDATA Synthesizer Control Interface The Synthesizer Control Interface allows the L64734 to control the L64733C frequency synthesizer. FDOUB Frequency Doubler Output, 3-State Bit 6 of register Group 4, APR 79 controls the L64734 FDOUB output pin, which enables or disables the frequency doubler on the L64733C. 20 L64733C/L64734 Tuner and Satellite Receiver Chipset The FDOUB pin is set as shown below; Fswitch is the frequency that disables or enables the frequency doubler. Frequency 925 MHz-Fswitch Fswitch-1680 MHz 1680-2175 MHz FDOUB APR 79[6] 0 1 1 TRI APR 79[2] 0 1 0 FDOUB Pin LOW 3-state HIGH MODp, MODn Modulus Selector Output The MODp and MODn signals are low-voltage differential signals from the L64734 of modulus selector programmable counter (A). PSOUT clocks these signals. When the MODp signal is positive with respect to the MODn signal, divide-by-32 is selected at the dual modulus prescaler on the L64733C Tuner IC. When MODp is negative with respect to MODn, divide-by-33 is selected. The counter A can be programmed to count down from a particular value by register bit programming. PLLINp, PLLINn PLL Differential Counter M Output The PLLINp and PLLINn signals are low-voltage differential signals from the L64734 programmable synthesizer counter (M). PSOUT clocks these signals. PLLINp is positive with respect to PLLINn for one PSOUT cycle. The repetition rate is 0.5 MHz for a 4 MHz reference crystal. The counter M can be programmed to count down from a particular value by register bit programming. PSOUTp, PSOUTn Prescaler Output Output The PSOUTp and PSOUTn signals are differential signals to the L64734 from the L64733C. The programmable counters on the L64734 are clocked on the rising edge of the PSOUT signal. In the external PLL mode (LOBUF = HIGH), these signals come from the LO buffer, for which the LODIV signal sets the divider ratio. RESO_LVDS LVDS Buffers Precision Resistor Output The RESO_LVDS output must be connected to a resistor (6.8 k, which controls the swing of the LVDSOUT L64733C/L64734 Tuner and Satellite Receiver Chipset 21 buffers used to drive the differential signals MODp, MODn, and PLLINp, PLLINn. Connect the other side of the resistor to ground. VREF_LVDS LVDS Buffers Reference Voltage Input The VREF_LVDS input is a 1.2 V 10% voltage level that controls the common mode voltage of the LVDSOUT buffers used to drive the differential signals MODp, MODn, and PLLINp, PLLINn. Tuner Control Interface The Tuner Control Interface contains signals that control the L64733C Tuner IC. FLCLK Filter Control Clock Output This is the output of a programmable integer value divider clocked by PCLK (the demodulator sampling clock). The division ratio can be programmed with register bits. The FLCLK frequency multiplied by 16 is the 3 dB cutoff of the programmable low pass filters on the L64733C. RF Input Select Output When INSEL is asserted, the L64733C tuner selects the normal mode. When INSEL is deasserted, the L64733C selects the Loop-Through mode. INSEL Typical Operating Circuit Figure 7 is a diagram of a typical operating circuit for the chipset, implemented with the L64733C-48 (48-pin package), including external components. Not all external components are shown. See the L64733/34 Evaluation Board User's Guide for complete schematic details. 22 L64733C/L64734 Tuner and Satellite Receiver Chipset Figure 7 Typical Operating Circuit 28 V 22 k 1 k 1 nF Stripline Inductors (2) Varactors (2) 6.8 k 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 22 nF 10 k SADR[1] SADR[0] VDD VSS SDATA SCLK INTn RESET VDD VSS PSOUTn PSOUTp VDD VSS PLLINn PLLINp RESO_LVD S 100 VREF_LVD BC847 1 k 37 38 39 40 41 42 43 44 45 46 47 48 24 24 100 pF VCC PSOUTp PSOUTn VCC GND1 GND1 TANKn VRLO TANKp VCC GND1 FB 180 pF 0.2 F 100 pF 47 pF 5 MHz L64733C-48 L64734 75 100 pF 47 k 1 2 3 4 5 6 7 8 9 10 11 12 0.1 F VCC CFLT XTLn XTLp GND1 VCC RFINn RFINp GND1 GNDSUB1 QDCn INSEL AGC2 AGC1 CPG2 XTLOUT VCC CPG1 RFOUT GND1 LOBUF IDCp AGC Filter PLLINn PLLINp MODn MODp LODIV IOUTp IOUTn VCC QOUTp QOUTn FDOUB 36 35 34 33 32 31 30 29 28 27 26 25 75 24 23 22 21 20 19 18 17 16 15 14 13 100 pF 0.1 F L64733C/L64734 Tuner and Satellite Receiver Chipset 0.01 F 75 100 pF 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 VDD VSS ADCVDDI IVINp IVINn ADCVSSI FBUFVDD IBIAS FBUFVSS ADCVDDQ QVINp QVINn ADCVSSQ VDD VSS FDOUB FLCLK INSEL AGC2 AGC1 VDD VSS XCTR[1] XCTR[0] XCTR[2] XCTR[3] XCTR_IN VDD VSS VDD PLLVSS LP2 PLLAGND PLLVDD PCLK LCLK VSS VDD CO[0] CO[1] CO[2] CO[3] VSS VDD CO[4] CO[5] CO[6] CO[7] VSS VDD BCLKOUT DVALIDOUT FSTARTOUT ERROROUTn VSS 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 XOOUT XOIN VSS CLK VDD QBYPASS[0 ] QBYPASS[1 ] VSS VDD QBYPASS[2 ] QBYPASS[3 ] QBYPASS[4 ] QBYPASS[5 ] Notes: 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 1. The ground connections for the L64733C are provided via a metal plate under the IC, rather than by direct connection of the ground pins to the PCB. 2. Not all external components are shown. Refer to the L64733/34 Evaluation Board User's Guide for complete details. 23 Specifications This section contains the electrical, timing, and mechanical specifications for the L64733C/734 chipset. L64733C Electrical Specifications Table 1 lists the absolute maximum values. Exceeding the values listed can cause damage to the L64733C. Table 2 gives the recommended operating supply voltage and temperature. Table 3 gives the DC characteristics; Table 4 gives the AC characteristics; and Table 5 and Table 6 summarize the pins for the 48- and 44-pin packages, respectively. Table 1 L64733C Absolute Maximum Rating (Referenced to VSS) Limits1 -0.5 to +7.0 1.8 27 0 to +70 +150 -65 to +165 +300 Units V W mW/C C C C C Symbol Parameter VCC - - - - - - DC supply voltage Continuous power dissipation up to +70 C Derating above +70 C Operating temperature Junction temperature Storage Temperature Lead temperature (soldering 10 sec) 1. Note that the ratings in this table are those beyond which permanent device damage is likely to occur. Do not use these values as the limits for normal device operation. Table 2 Recommended Operating Conditions Limits1 Units 5 5% 70 V C Symbol Parameter VDD TA DC Supply Voltage Operating Ambient Temperature Range (Commercial) 1. For normal device operation, adhere to the limits in this table. Sustained operation of a device at conditions exceeding these values, even if they are within the absolute maximum rating limits, can result in permanent device damage or impaired device reliability. Device functionality to stated DC and AC limits is not guaranteed if recommended operating conditions are exceeded. 24 L64733C/L64734 Tuner and Satellite Receiver Chipset Table 3 Parameter DC Characteristics of the L64733C Condition Min Typ Max Units Power Supply Power Supply Voltage Power Supply Current All DC specs met 4.75 - 5.0 195 5.25 275 V mA Digital Control Inputs - CPG1, CPG2, INSEL, FDOUB, LOBUF, LODIV Input Logic Level High Input Logic Level Low Input Bias Current Pin at 2.4 V 2.4 0 -15 - - - - 0.5 10 V V A Slew-Limited Digital Clock Inputs - FLCLK FLCLK Input Level Low FLCLK Input Level High FLCLK Input Resistance/Leakage Current 50 k series resistor between L64734 and FLCLK pin. L64734 generates normal CMOS levels - 1.85 -1 - - - 1.45 - 1 V V A Fast Digital Clock Inputs - MODp, MODn, PLLINp, PLLINn MODp, MODn, PLLINp, PLLINn Common Mode Input Range (VCM) MODp, MODn, PLLINp, PLLINn Input Voltage Low MODp, MODn, PLLINp, PLLINn Input Voltage High MODp, MODn, PLLINp, PLLINn Input Current MODp, MODn, or PLLINp, PLLINn differential swing around VCM. Need external 100- termination. MODp, MODn, or PLLINp, PLLINn differential swing around VCM. Need external 100- termination MODp, MODn, PLLINp, PLLINn 1.08 1.2 1.32 V - - -100 mV 100 - - mV -5 - +5 A Digital Clock Outputs - PSOUTp, PSOUTn PSOUTp, PSOUTn Common Mode Output Range (VCM) PSOUTp, PSOUTn Output Voltage Low PSOUTp, PSOUTn differential swing around VCM. Driving LSI PECL Load (10 A), LOBUF = 0 2.16 - 2.4 -215 2.64 -150 V mV (Sheet 1 of 3) L64733C/L64734 Tuner and Satellite Receiver Chipset 25 Table 3 Parameter DC Characteristics of the L64733C (Cont.) Condition PSOUTp, PSOUTn differential swing around VCM. Driving LSI PECL Load (10 A), LOBUF = 0 PSOUTp, PSOUTn differential swing around VCM, driving 100 differential LOBUF = 1 PSOUTp, PSOUTn differential swing around VCM, driving 100 differential. LOBUF is asserted. Min 150 Typ 215 Max - Units mV PSOUTp, PSOUTn Output Voltage High PSOUTp, PSOUTn Output Voltage Low PSOUTp, PSOUTn Output Voltage High - -140 -100 mV 100 140 - mV Synthesizer/Local Oscillator Buffer Prescaler Ratio MOD = High MOD = Low LO Buffer Division Ratio LOBUF = High, LODIV = Low LOBUF = High, LODIV = High Reference Divider Ratio Charge Pump Output High Current (at FB) CPG1, CPG2 = 0, 0 CPG1, CPG2 = 0, 1 CPG1, CPG2 = 1, 0 CPG1, CPG2 = 1, 1 Charge Pump Output Low Current (at FB) CPG1, CPG2 = 0, 0 CPG1, CPG2 = 0, 1 CPG1, CPG2 = 1, 0 CPG1, CPG2 = 1, 1 Charge Pump Output Leakage Current Charge Pump Positive-to-Negative Current Matching Charge Pump Output Transistor Base Current Drive (Sheet 2 of 3) FB self-biased. 8 0.08 0.24 0.48 1.44 -0.12 -0.36 -0.72 -2.16 -25 -5 32 33 - - 2 1 - 0.1 0.3 0.6 1.8 -0.1 -0.3 -0.6 -1.8 - - 8 0.12 0.36 0.72 2.16 -0.08 -0.24 -0.48 -1.44 25 5 32 33 - - - - - mA mA mA mA mA mA mA mA nA % 100 - - A 26 L64733C/L64734 Tuner and Satellite Receiver Chipset Table 3 Parameter DC Characteristics of the L64733C (Cont.) Condition Min Typ Max Units Analog Control Inputs - AGC1, AGC2 Input Bias Current 1 V < Pin < 4 V -50 -- 50 A Baseband Outputs - IOUTp, IOUTn, QOUTp, QOUTn Output Swing IOUTp, IOUTn, QOUTp, QOUTn Common Mode Voltage IOUTp, IOUTn, QOUTp, QOUTn DC Offset Voltage (Sheet 3 of 3) Loaded with 2 k differential across IOUTp, IOUTn, and QOUTp, QOUTn 1 0.65 -- -- -- 0.85 VPP V -50 -- 50 mV Table 4 Parameter AC Characteristics of the L64733C Condition Min Typ Max Units RF Front End RFIN Input Freq. Range RFIN Single-Carrier Input Power1 AGC1 Range AGC2 Range RFIN referred IP3 (front-end contributions) Meets all following AC specs RF level needed to produce 0.59 VPP. 1 V < AGC1 < 4 V 1 V < AGC2 < 4 V AGC1 gain set for -25 dBm input level (0.59 VPP output), and AGC2 set to maximum gain (VAGC2 = 1 V). Two signals at FLO + 32 MHz, FLO + 72 MHz @2175 MHz @1550MHz @925 MHz 925 -68 50 19 - - - - - - - 10.5 11.5 10.5 2175 -25 - - - - - MHz dBm dB dB dBm dBm dBm Baseband 1 dB Compression Point RFIN Referred IP2 (Sheet 1 of 3) IOUTp, IOUTn, QOUTp, QOUTn have one signal within filter bandwidth PRFIN = -25 dBm, FLO = 951 MHz 2 - - 15.5 - - VPP dBm L64733C/L64734 Tuner and Satellite Receiver Chipset 27 Table 4 Parameter Noise Figure AC Characteristics of the L64733C (Cont.) Condition At maximum gain AGC1, AGC2, 2150 MHz Complex "75 source" subject to board, connector parasitics. 950 MHz to 2150 MHz, subject to board layout Due to LO-generated 2nd harmonic Due to RFIN-generated 2nd harmonic Min - - - - - Typ 10.8 11 -65 44 40 Max - - - - - Units dB dB dBm dB dB RFIN Return Loss LO Leakage Power at RFIN Second Harmonic Rejection Half-Harmonic Rejection and x 1.5 Harmonic Rejection2 Loop Through Gain @2175 MHz @1550MHz @925 MHz At PRFIN = -25 dBm @2175 MHz @1550MHz @925 MHz - 2.0 1.0 0.5 5.4 7.7 9.5 12.0 8 - dB RFIN referred IP3 (when Loop-Through enabled) Noise Figure Return Loss Baseband - - dBm - Subject to board and connector parasitics - - - dB dB IOUTp, IOUTn, QOUTp, 2 k differential load, IOUTp, IOUTn, QOUTn Differential Output QOUTp, QOUTn. Expect 20 pF from Voltage Swing each pin to GND IOUTp, IOUTn, QOUTp, Per side, IOUTp, IOUTn, QOUTp, QOUTn Output Impedance QOUTn. To 200 MHz Baseband Highpass -3 dB 0.22 F caps connected from IDCp to Point IDCn, and QDCp to QDCn. LPF Nominal Cutoff Frequency Range LPF Nominal Fc Fc is -3 dB point of filter 1 - - VPP - - 8 - - - - 14.5 * FFLCLK + 1 50 750 33 - Hz MHz - (Sheet 2 of 3) 28 L64733C/L64734 Tuner and Satellite Receiver Chipset Table 4 Parameter AC Characteristics of the L64733C (Cont.) Condition Deviation from ideal 7th-order Butterworth, measure to F - 3 dB x 0.7. Include front-end tilt effects Measured -3 dB point. @8 MHz @31.4 MHz Min -0.5 Typ - Max 0.5 Units dB Baseband Frequency Response LPF Cutoff Frequency Accuracy Quadrature Gain Error Quadrature Phase Error Synthesizer Crystal Frequency Range XTLOUT Voltage Levels XTLOUT DC Level MODp, MODn Delay -5.5 -10 - - - - - - 5.5 10 1.2 4 % % dB Deg Includes effects from baseband filters Measure at 125 kHz 4 Measured on 10 pF in parallel with 1 M 0.75 - Must assert MOD level within this time period to ensure that the next PSOUT period gives correct count. Delay is with respect to rising edge of PSOUT (previous count). With respect to rising edge of PSOUT. This means that PSOUT need not continue to be asserted after MOD has given correct count. - - 1.0 2.0 - 7.26 1.5 - 7 MHz Vpp V nsec PLLINp, PLLINn and MODp, MODn Hold Time 0 - - nsec Local Oscillator LO Tuning Range LO Phase Noise, Including 1 kHz offset. Depends on PLL loop Doubler. Subject to LC tank gain. implementation. 10 kHz offset. Depends on PLL loop gain. 100 kHz offset LO Buffer Frequency FDOUB = low Range when overdriven by external LO (Sheet 3 of 3) For symbol rates below 15 MS/s, the maximum input power might be subject to shifting down by roughly 10 * log(15/Rs[MS/s]) dB due to channel bandwidth reduction. 2. x 1.5 harmonic rejection for FLO = 725 MHz. 1. 543 - - - 925 - -55 -75 -95 - 1180 - - - 2175 MHz dBc/Hz dBc/Hz dBc/Hz MHz L64733C/L64734 Tuner and Satellite Receiver Chipset 29 Table 5 Mnemonic AGC1 AGC2 CFLT CP CPG[2:1] FB FDOUB FLCLK GND IDCp IDCn INSEL IOUTp IOUTn LOBUF LODIV MODp MODn PLLINp PLLINn PSOUTp PSOUTn QDCp L64733C-48 Pin Description Summary Description Automatic Gain Control 1 Automatic Gain Control 2 Bias Voltage Bypass Charge Pump Charge Pump Gain Feedback Charge Pump Transistor Drive Frequency Doubler Filter Clock Ground (seven pins total) I-Channel DC Offset Correction (noninverting) I-Channel DC Offset Correction (inverting) RF Port Input Select I-Channel Baseband Data (noninverting) I-Channel Baseband Data (inverting) Local Oscillator Buffer Select Local Oscillator Buffer Division Ratio Select Prescaler Modulus (noninverting) Prescaler Modulus (inverting) Phase Detector (noninverting) Phase Detector (inverting) Prescaler (noninverting) Prescaler (inverting) Q-Channel DC Offset Correction (noninverting) Type Input Input Bidirectional Output Input Output Input Input Input Input Input Input Output Output Input Input Input Input Input Input Output Output Input (Sheet 1 of 2) 30 L64733C/L64734 Tuner and Satellite Receiver Chipset Table 5 Mnemonic QDCn QOUTp QOUTn RFINp RFINn RFOUT TANKp TANKn VCC VRLO XTLp XTLn XTLOUT L64733C-48 Pin Description Summary (Cont.) Description Q-Channel DC Offset Correction (inverting) Q-Channel Baseband Data (noninverting) Q-Channel Baseband Data (inverting) RF Input (noninverting) RF Input (inverting) RF Output (Loop-Through) Oscillator Tank Port (noninverting) Oscillator Tank Port (inverting) Power (six pins total) Local Oscillator Regulator Bypass Crystal Oscillator Port (noninverting) Crystal Oscillator Port (inverting) Crystal Out Type Input Output Output Input Input Output Input Input Input Bidirectional Input Input Output (Sheet 2 of 2) L64733C/L64734 Tuner and Satellite Receiver Chipset 31 Table 6 Mnemonic AGC1 AGC2 CFLT CP CPG[2:1] FB FDOUB FLCLK GND IDCp IDCn INSEL IOUTp IOUTn LOBUF LODIV MODp MODn PLLINp PLLINn PSOUTp PSOUTn QDCp L64733C-44 Pin Description Summary Description Automatic Gain Control 1 Automatic Gain Control 2 Bias Voltage Bypass Charge Pump Charge Pump Gain Feedback Charge Pump Transistor Drive Frequency Doubler Filter Clock Ground (three pins total) I-Channel DC Offset Correction (noninverting) I-Channel DC Offset Correction (inverting) RF Port Input Select I-Channel Baseband Data (noninverting) I-Channel Baseband Data (inverting) Local Oscillator Buffer Select Local Oscillator Buffer Division Ratio Select Prescaler Modulus (noninverting) Prescaler Modulus (inverting) Phase Detector (noninverting) Phase Detector (inverting) Prescaler (noninverting) Prescaler (inverting) Q-Channel DC Offset Correction (noninverting) Type Input Input Bidirectional Output Input Output Input Input Input Input Input Input Output Output Input Input Input Input Input Input Output Output Input (Sheet 1 of 2) 32 L64733C/L64734 Tuner and Satellite Receiver Chipset Table 6 Mnemonic QDCn QOUTp QOUTn RFINp RFINn RFOUT TANKp TANKn VCC VRLO XTLp XTLn XTLOUT L64733C-44 Pin Description Summary (Cont.) Description Q-Channel DC Offset Correction (inverting) Q-Channel Baseband Data (noninverting) Q-Channel Baseband Data (inverting) RF Input (noninverting) RF Input (inverting) RF Output (Loop-Through) Oscillator Tank Port (noninverting) Oscillator Tank Port (inverting) Power (six pins total) Local Oscillator Regulator Bypass Crystal Oscillator Port (noninverting) Crystal Oscillator Port (inverting) Crystal Out Type Input Output Output Input Input Output Input Input Input Bidirectional Input Input Output (Sheet 2 of 2) L64734 Electrical Specifications This section contains the electrical parameters for the L64734. Table 7 lists the absolute maximum values. Exceeding the values listed can cause damage to the L64734. Table 8 gives the recommended operating supply voltage and temperature conditions. Table 9 shows the pin capacitance, Table 10 gives the DC characteristics, and Table 11 summarizes the pins. L64733C/L64734 Tuner and Satellite Receiver Chipset 33 Table 7 L64734 Absolute Maximum Rating (Referenced to VSS) Limits1 -0.3 to + 3.9 -1.0 to VDD + 0.3 -1.0 to 6.5 10 -40 to +125 Units V V V mA C Symbol Parameter VDD VIN VIN IIN TSTG DC Supply Voltage LVTTL Input Voltage 5 V Compatible Input Voltage DC Input Current Storage Temperature Range (Plastic) 1. Note that the ratings in this table are those beyond which permanent device damage is likely to occur. Do not use these values as the limits for normal device operation. Table 8 L64734 Recommended Operating Conditions Limits1 +3.14 to 3.47 0 to +70 +125 7 Units V C C C/watt Symbol Parameter VDD TA Tj jc DC Supply Voltage Operating Ambient Temperature Range (Commercial) Junction Temperature Junction to Case Thermal Resistance2 1. For normal device operation, adhere to the limits in this table. Sustained operation of a device at conditions exceeding these values, even if they are within the absolute maximum rating limits, can result in permanent device damage or impaired device reliability. Device functionality to stated DC and AC limits is not guaranteed if recommended operating conditions are exceeded. 2. The junction to case thermal resistance is valid for measurements in an isothermal environment including the board and package. Table 9 Symbol CIN COUT L64734 Capacitance Parameter1 Input Capacitance Output Capacitance Max 5 5 Units pF pF 1. Measurement conditions are VIN = 3.3 V, TA = 25 C, and clock frequency = 1 MHz. 34 L64733C/L64734 Tuner and Satellite Receiver Chipset Table 10 Symbol VDD VIL VIH DC Characteristics of the L64734 Parameter Supply Voltage Input Voltage LOW Input Voltage HIGH LVTTL Com/Ind/Mil Temp Range 5 V compatible Condition1 Min 3.0 VSS - 0.5 2.0 2.0 - VDD = Max, VIN = VDD or VSS VIN = VSS VIN = VDD IOH = -1.0, -2.0, -4.0, -6.0, -8.0, -12.0 mA IOH = 1.0, 2.0, 4.0, 6.0, 8.0, 12.0 mA VDD = Max, VOUT = VSS or 3.5 V VIN = VDD or VSS - - PSOUTp - PSOUTn = 50 mV VCM + 50 mV -10 -62 -62 2.4 -- -10 - 290 2.4 - Typ 3.3 - - - 1.4 1 -215 -215 - 0.2 1 Max 3.6 0.8 VDD + 0.3 5.5 2.0 10 -384 -384 VDD 0.4 10 2 - - - Units V V V V V A A A V V A mA mA V V VT IIL IIPU IIPD VOH VOL IOZ IDD ICC VCM VIH_PECL Switching Threshold Input Current Leakage Input Current Leakage with Pull-up Input Current Leakage with Pull-down Output Voltage HIGH Output Voltage LOW 3-State Output Leakage Current Quiescent Supply Current Dynamic Supply Current f = MHz, VDD = Max Midpoint of PSOUTp, PSOUTn inputs Input Voltage High Level (DC) (Sheet 1 of 2) L64733C/L64734 Tuner and Satellite Receiver Chipset 35 Table 10 Symbol VIL_PECL IIL_PECL IIH_PECL DC Characteristics of the L64734 (Cont.) Parameter Input Voltage Low Level (DC) Input Low Current Input High Current Condition1 PSOUTp - PSOUTn = 50 mV VIN = VSS VIN = VDD Min - -10 - - On PLLINp/PLLINn, MODp/MODn signals On PLLINp/PLLINn, MODp/MODn signals 1.253 1.030 Typ - - - 1.2 1.373 1.032 Max VCM - 50 mV - +10 - 1.437 1.059 Units V A A V V V VRESO_LVDS Output Voltage on pin RESO_LVDS VOH_LVDS VOL_LVDS Output Voltage High Level (DC) Output Voltage Low Level (DC) (Sheet 2 of 2) 1. Specified at VDD = 3.3 V 5% at ambient temperature over the specified range. Table 11 Mnemonic ADCVDDI/Q ADCVSSI/Q AGC1, AGC2 BCLKOUT CLK CO[7:0] COEn DVALIDOUT L64734 Pin Description Summary Description ADC Power ADC Analog Ground Power Control Byte Clock Out IVIN/QVIN Input Clock Channel Data Out Channel Output Enable Valid Data Out Error Detection Flag Analog Supply Analog Ground Type Input Input Outputs Output Input Output Input Output Output Input Input ERROROUTn FBUFVDD FBUFVSS (Sheet 1 of 3) 36 L64733C/L64734 Tuner and Satellite Receiver Chipset Table 11 Mnemonic FDOUB FLCLK FSTARTOUT IBIAS IBYPASS[5:0] IDDTN INSEL INTn IVINn, IVINp LCLK LP2 L64734 Pin Description Summary (Cont.) Description Frequency Doubler Filter Control Clock Frame Start Output ADC Bias Current I Channel Data (ADC bypassed) Test RF Input Select Interrupt I Channel Data Decimated Clock Output Input to VCO Modulus Selector PLL Clock Output PLL Analog Ground PLL Differential Counter M PLL Power PLL Ground Type Output, 3-State Output Output Output Inputs Input Output Output Input Output Input Outputs Output Input Outputs Input Input Outputs Input Input Input Output Input Bidirectional MODp, MODn PCLK PLLAGND PLLINn, PLLINp PLLVDD PLLVSS PSOUTp, PSOUTn Prescaler Output QBYPASS[5:0] QVINn, QVINp RESET RESO_LVDS SADR[1:0] SCLK (Sheet 2 of 3) Q Channel Data (ADC bypassed) Q Channel Data Reset LVDS Buffers Precision Resistor Serial Address Serial Clock L64733C/L64734 Tuner and Satellite Receiver Chipset 37 Table 11 Mnemonic SDATA VREF_LVDS XCTR_IN XCTR[3:0] XOIN XOOUT L64734 Pin Description Summary (Cont.) Description Serial Data LVDS Buffers Reference Voltage Control Input Control Output/Sync Status Flag Crystal Oscillator In Crystal Oscillator Out Type Bidirectional Input Input Output Input Output (Sheet 3 of 3) This section includes AC timing information for the L64734. During AC testing, HIGH inputs are driven to 3.0 V and LOW inputs are driven to 0 V. For transitions between HIGH, LOW, and invalid states, timing measurements are made at 1.5 V, as shown in Figure 8. Figure 8 AC Test Load and Waveform for Standard Outputs Test Point Output CL = 15 pF 1.5 V For 3-state outputs, timing measurements are made from the point at which the output turns ON or OFF. An output is ON when its voltage is greater than 2.5 V or less than 0.5 V. An output is OFF when its voltage is less than VDD - 0.5 V or greater than 0.5 V, as shown in Figure 9. 38 L64733C/L64734 Tuner and Satellite Receiver Chipset Figure 9 Test Point AC Test Load and Waveforms for 3-State Outputs Iref = 20 mA Output Vref = 1.5 V Vref 2.5 V 0.5 V VDD -0.5 V 0.5 V 55 pF Iref = -20 mA Synchronous timing is shown in Figure 10. Synchronous inputs must have a setup and hold relationship with respect to the clock signal that samples them. Synchronous outputs have a delay from the clock edge that asserts them. Figure 10 L64734 Synchronous AC Timing 1 2 PCLK CLK 5 INPUTS 6 OUTPUTS 4 3 The reset pulse requirements are shown in Figure 11. Figure 11 L64734 RESET Timing Diagram 7 RESET 8 Figure 12 shows the relationship of the L64734 3-state signals to the COEn signal. L64733C/L64734 Tuner and Satellite Receiver Chipset 39 Figure 12 COEn L64734 Bus 3-State Delay Timing 9 CO FSTARTOUT ERROROUTn DVALIDOUT BCLKOUT 9 Figure 13 shows the relationship of the L64733C PSOUTp and PSOUTn prescaler signals to the signals fed back to the L64733C from the L64734 to control the synthesizer. Figure 13 L64734 Synchronous AC Timing - Synthesizer Control 10 11 PSOUTp PSOUTn 13 PLLINp, MODp PLLINn, MODn 12 The numbers in the first column of Table 12 refer to the timing parameters shown in the preceding figures. All parameters in the timing tables apply for TA = 0 C to 70 C and a capacitive load of 15 pF. 40 L64733C/L64734 Tuner and Satellite Receiver Chipset Table 12 L64734 AC Timing Parameters 90 MHz Parameter 1 2 3 4 5 6 6 7 8 9 10 11 12 tCYCLE tPWH tPWL tS tH tODS tODP tRWH tWK TDLY tCYCLE_PS tPWH_PS tPWL_PS Description Clock Cycle for PCLK Clock Pulse Width HIGH Clock Pulse Width LOW Input Setup Time to CLK Input Hold to CLK Output Delay from PCLK, serial mode Output Delay from BCLKOUT, parallel mode Reset Pulse Width HIGH Wake-Up Time Delay from COEn Clock Cycle for PSOUTp, PSOUTn clock PSOUT Clock Pulse Width HIGH PSOUT Clock Pulse Width LOW Min Max Units ns ns ns ns ns ns PCLK cycles CLK cycles CLK cycles ns ns ns ns 11.1 33.31 6 5 4 4 3 3 3 280 - 14 6 6 - - - - 8 - - - 6 35 - - 1. Minimum Fs (sampling clock = 30 MHz). L64733C/L64734 Tuner and Satellite Receiver Chipset 41 L64733C/734 Chipset Ordering Information The L64733C-48 is available in a 48-pin TQFP package, the L64733C-44 is available in a 44-pin MLF2 package, and the L64734 is available in a 100-pin PQFP package. They are ordered as a set. Table 13 gives ordering information for the chipset. Table 13 L64733C/734 Chipset Ordering Information Package Type Operating Range Commercial Order Number Kit 733x 734y x = 733 version 48-pin TQFP (L64733C-48) 44-pin MLF2 (L64733C-44) y = 734 version 100-pin PQFP (L64734) The tables and figures that follow provide pinouts and mechanical drawings for each package in the chipset. 42 L64733C/L64734 Tuner and Satellite Receiver Chipset L64733C-48 Pinout and Packaging Information The following subsections provide pinout and packaging information for the 48-pin L64733C chip. L64733C-48 Pinouts Figure 14 gives the pinout for the 48-pin TQFP L64733C-48 package. Figure 14 L64733C 48-Pin TQFP Pinout PSOUTp PSOUTn VCC GND GND TANKn VRLO TANKp VCC GND FB CP VCC CFLT XTLn XTLp GND VCC RFINn RFINp GND GNDSUB QDCn QDCp 1 2 3 4 5 6 7 8 9 10 11 12 L64733C/L64734 Tuner and Satellite Receiver Chipset 37 38 39 40 41 42 43 44 45 46 47 48 Top View 36 35 34 33 32 31 30 29 28 27 26 25 PLLINn PLLINp MODn MODp LODIV IOUTp IOUTn VCC QOUTp QOUTn FDOUB FLCLK 24 23 22 21 20 19 18 17 16 15 14 13 INSEL AGC2 AGC1 CPG2 XTLOUT VCC CPG1 RFOUT GND LOBUF IDCp IDCn 43 L64733C-48 Mechanical Drawing Figure 15 is a mechanical drawing for the 48-pin TQFP L64733C-48 package. Figure 15 L64733C-48 48-pin TQFP Mechanical Drawing TOP VIEW D D/2 D1 D1/2 E1/2 A e E E1 .15 MIN. BOTTOM VIEW .50 MAX. EXPOSED PAD CORNER TAB DETAIL EVEN LEAD SIDES E/2 SEE DETAIL "A" e/2 8 PLACES 11-13 A 0 MIN. M DATUM PLANE -H0.08 R. MIN. 0-7 0.20 MIN. 0.09/0.20 b 0.09/0.16 1.00 REF. DETAIL "B" L DETAIL "A" SEE DETAIL "B" A2 0.08/0.20 R. 0.25 GAUGE PLANE b WITH LEAD FINISH A1 1 BASE METAL Notes: 1. All dimensioning and tolerancing conform to Ansi Y14.5-1982. 2. Datum plane - H - is located at mold parting line and coincident with lead, where lead exits plastic body at bottom of parting line. 3. Dimensions D1 and E1 do not include mold protrusion. allowable mold protrusion is 0.254 mm on D1 and E1 dimensions. 4. The top of package is smaller than the bottom of package by 0.15 millimeters. 5. Dimension B does not include dambar protrusion. Allowable dambar protrusion shall be 0.08 mm total in excess of the B dimension at maximum material condition. 6. Controlling dimension: millimeter. 7. Maximum allowable die thickness to be assembled in this package family is 0.30 millimeters. 8. This outline conforms to Jedec Publication 95 Registration MO-136, variations AC and AE. 9. Exposed die pad shall be coplanar with bottom of package within 2 mils (0.05 mm). 10. Metal area of exposed die pad shall be within 0.3 mm of the nominal die pad size. S Y M B O L JEDEC VARIATION ALL DIMENSIONS IN MILLIMETERS AE MIN. 0.05 0.95 NOM. 0.10 1.00 9.00 BSC. 7.00 BSC. 9.00 BSC. 7.00 BSC. 0.60 48 0.5 BSC. 0.22 0.20 MAX. 1.20 0.15 1.05 A A1 A2 D D1 E E1 L M N e b b1 0.45 0.14 0.17 0.17 0.75 0.27 0.23 44 L64733C/L64734 Tuner and Satellite Receiver Chipset L64733C-44 Pinout and Packaging Information The following subsections provide pinout and packaging information for the 44-pin L64733C chip. L6433C-44 Pinout Figure 16 gives the pinout for the 44-pin QFN L64733-44 package. Figure 16 L64733 44-Pin QFN Pinout CP VTUNE VCC VCC NC VRLO NC NC VCC PSOUTn PSOUTp 44 43 42 41 40 39 38 37 36 35 34 L64733C/L64734 Tuner and Satellite Receiver Chipset IDCn IDCp NC LOCK CPG1/VCO0 VCC XTALOUT CPG2/VCO1 AGC1 AGC2 ICPHI/VCO2 12 13 14 15 16 17 18 19 20 21 22 XTALn XTALp CFLT VCC NC VCC RFINn RFINp NC QDCn QDCP 1 2 3 4 5 6 7 8 9 10 11 L6473 44 Pin QFN Top View 33 32 31 30 29 28 27 26 25 24 23 PLLINn PLLINp MODn MODp IOUTp IOUTn VCC QOUTp QOUTn FDIV FLCLK 45 L64733C-44 Mechanical Drawings Figure 17 is a mechanical drawing for the 44-pin QFN L64733-44 package. Figure 17 L64733C-44 44-pin QFN Mechanical Drawing 46 L64733C/L64734 Tuner and Satellite Receiver Chipset Figure 17 L64753-44 44-pin QFN Mechanical Drawing (Cont.) L64733C/L64734 Tuner and Satellite Receiver Chipset 47 L64734 Pinout and Packaging Information The following subsections provide pinout and packaging information for the L64734. L64734 Pinouts Figure 18 gives the pinout for the 100-pin PQFP L64734 package. Figure 18 L64734 100-Pin PQFP Pinout VSS VDD PLLVSS LP2 PLLAGND PLLVDD PCLK LCLK VSS VDD CO[0] CO[1] CO[2] CO[3] VSS VDD CO[4] CO[5] CO[6] CO[7] VSS VDD BCLKOUT DVALIDOUT FSTARTOUT ERROROUTn VSS VDD COEn IDDTN 48 VDD VSS ADCVDDI IVINp IVINn ADCVSSI FBUFVDD IBIAS FBUFVSS ADCVDDQ QVINp QVINn ADCVSSQ VDD VSS FDOUB FLCLK INSEL AGC2 AGC1 VDD VSS XCTR[1] XCTR[0] XCTR[2] XCTR[3] XCTR_IN VDD VSS IBYPASS[5] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 SADR[1] SADR[0] VDD VSS SDATA SCLK INTn RESET VDD VSS PSOUTn PSOUTp VDD VSS PLLINn PLLINp RESO_LVDS VREF_LVDS MODn MODp 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 Top View XOOUT XOIN VSS CLK VDD QBYPASS[0] QBYPASS[1] VSS VDD QBYPASS[2] QBYPASS[3] QBYPASS[4] QBYPASS[5] IBYPASS[0] VSS VDD IBYPASS[1] IBYPASS[2] IBYPASS[3] IBYPASS[4] L64733C/L64734 Tuner and Satellite Receiver Chipset L64734 Mechanical Drawings Figure 19 and Figure 20 show the mechanical drawings for the 100-pin PQFP L64734 package. Figure 19 100-pin PQFP (UD) Mechanical Drawing MD97.UD-1 Important: This drawing may not be the latest version. For board layout and manufacturing, obtain the most recent engineering drawings from your LSI Logic marketing representative. L64733C/L64734 Tuner and Satellite Receiver Chipset 49 Figure 20 100-pin PQFP (UD) Mechanical Drawing (Cont.) MD97.UD-2 Important: This drawing may not be the latest version. For board layout and manufacturing, obtain the most recent engineering drawings from your LSI Logic marketing representative by requesting the outline drawing for package code UD. 50 L64733C/L64734 Tuner and Satellite Receiver Chipset Notes L64733C/L64734 Tuner and Satellite Receiver Chipset 51 Sales Offices and Design Resource Centers LSI Logic Corporation Corporate Headquarters Tel: 408.433.8000 Fax: 408.433.8989 NORTH AMERICA California Irvine Tel: 949.809.4600 Fax: 949.809.4444 Pleasanton Design Center Tel: 925.730.8800 Fax: 925.730.8700 San Diego Tel: 858.467.6981 Fax: 858.496.0548 Silicon Valley Tel: 408.433.8000 Fax: 408.954.3353 Wireless Design Center Tel: 858.350.5560 Fax: 858.350.0171 Colorado Boulder Tel: 303.447.3800 Fax: 303.541.0641 Colorado Springs Tel: 719.533.7000 Fax: 719.533.7020 Fort Collins Tel: 970.223.5100 Fax: 970.206.5549 Florida Boca Raton Tel: 561.989.3236 Fax: 561.989.3237 Georgia Alpharetta Tel: 770.753.6146 Fax: 770.753.6147 Illinois Oakbrook Terrace Tel: 630.954.2234 Fax: 630.954.2235 Kentucky Bowling Green Tel: 270.793.0010 Fax: 270.793.0040 Maryland Bethesda Tel: 301.897.5800 Fax: 301.897.8389 Massachusetts Waltham Tel: 781.890.0180 Fax: 781.890.6158 Burlington - Mint Technology Tel: 781.685.3800 Fax: 781.685.3801 Minnesota Minneapolis Tel: 612.921.8300 Fax: 612.921.8399 New Jersey Red Bank Tel: 732.933.2656 Fax: 732.933.2643 Cherry Hill - Mint Technology Tel: 856.489.5530 Fax: 856.489.5531 New York Fairport Tel: 716.218.0020 Fax: 716.218.9010 North Carolina Raleigh Tel: 919.785.4520 Fax: 919.783.8909 Oregon Beaverton Tel: 503.645.0589 Fax: 503.645.6612 Texas Austin Tel: 512.388.7294 Fax: 512.388.4171 Korea Seoul LSI Logic Corporation of Korea Ltd Tel: 82.2.528.3400 Fax: 82.2.528.2250 The Netherlands Eindhoven LSI Logic Europe Ltd Tel: 31.40.265.3580 Fax: 31.40.296.2109 Singapore Singapore LSI Logic Pte Ltd Tel: 65.334.9061 Fax: 65.334.4749 Sweden Stockholm LSI Logic AB Tel: 46.8.444.15.00 Fax: 46.8.750.66.47 Taiwan Taipei LSI Logic Asia, Inc. Taiwan Branch Tel: 886.2.2718.7828 Fax: 886.2.2718.8869 United Kingdom Bracknell LSI Logic Europe Ltd Tel: 44.1344.426544 Fax: 44.1344.481039 Tel: 972.244.5000 Plano Fax: 972.244.5001 Houston Tel: 281.379.7800 Fax: 281.379.7818 Canada Ontario Ottawa Tel: 613.592.1263 Fax: 613.592.3253 INTERNATIONAL France Paris LSI Logic S.A. Immeuble Europa Tel: 33.1.34.63.13.13 Fax: 33.1.34.63.13.19 Germany Munich LSI Logic GmbH Tel: 49.89.4.58.33.0 Fax: 49.89.4.58.33.108 Tel: 49.711.13.96.90 Stuttgart Fax: 49.711.86.61.428 Italy Milan LSI Logic S.P.A. Tel: 39.039.687371 Fax: 39.039.6057867 Japan Tokyo LSI Logic K.K. Tel: 81.3.5463.7821 Fax: 81.3.5463.7820 Sales Offices with Design Resource Centers Tel: 81.6.947.5281 Osaka Fax: 81.6.947.5287 Visit us at our web site: http://www.lsilogic.com ISO 9000 Certified LSI Logic Corporation reserves the right to make changes to any products and services herein at any time without notice. LSI Logic does not assume any responsibility or liability arising out of the application or use of any product or service described herein, except as expressly agreed to in writing by LSI Logic; nor does the purchase, lease, or use of a product or service from LSI Logic convey a license under any patent rights, copyrights, trademark rights, or any other of the intellectual property rights of LSI Logic or of third parties. Printed in USA Order No. I15042 Doc. No. DB08-000162-00 LSI Logic logo design is a registered trademark of LSI Logic Corporation. All other brand and product names may be trademarks of their respective companies. |
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